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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>D:\Gowin\Gowin_V1.9.8.07_Education\IDE\ipcore\VFB\data\vfb_top.v<br>
D:\Gowin\Gowin_V1.9.8.07_Education\IDE\ipcore\VFB\data\vfb_wrapper.vp<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>GowinSynthesis V1.9.8.07 Education</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sat Sep 24 16:37:16 2022
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>Video_Frame_Buffer_Top</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.325s, Peak memory usage = 36.215MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 36.215MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 36.215MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 36.215MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 36.215MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 36.215MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 36.215MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 36.215MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 36.215MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 36.215MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 36.215MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 36.215MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 48.867MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.132s, Peak memory usage = 48.867MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.082s, Peak memory usage = 48.867MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 48.867MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>362</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>361</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>158</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>203</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>402</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFF</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFS</td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFR</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFP</td>
<td>16</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFPE</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFC</td>
<td>254</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>110</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFNP</td>
<td>8</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>797</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>202</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>321</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>274</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>38</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>38</td>
</tr>
<tr>
<td class="label"><b>SSRAM </b></td>
<td>6</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspRAM16S4</td>
<td>6</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>4</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPB</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPX9B</td>
<td>7</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>875(801 LUTs, 38 ALUs, 6 SSRAMs) / 20736</td>
<td>4%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>402 / 16173</td>
<td>2%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>402 / 16173</td>
<td>2%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>8 / 46</td>
<td>17%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>I_vin0_clk</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>I_vin0_clk_ibuf/I </td>
</tr>
<tr>
<td>I_dma_clk</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>I_dma_clk_ibuf/I </td>
</tr>
<tr>
<td>I_vout0_clk</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>I_vout0_clk_ibuf/I </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>I_vin0_clk</td>
<td>100.0(MHz)</td>
<td>225.9(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>I_dma_clk</td>
<td>100.0(MHz)</td>
<td>152.9(MHz)</td>
<td>10</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>I_vout0_clk</td>
<td>100.0(MHz)</td>
<td>190.2(MHz)</td>
<td>9</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.460</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.367</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_dma_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>I_dma_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_dma_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_dma_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>217</td>
<td>I_dma_clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>8</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s12/AD[0](chk_dup)</td>
</tr>
<tr>
<td>1.849</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s12/DO[0]</td>
</tr>
<tr>
<td>2.086</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_7_s2/I1</td>
</tr>
<tr>
<td>2.641</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_7_s2/F</td>
</tr>
<tr>
<td>2.878</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s0/I2</td>
</tr>
<tr>
<td>3.331</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s0/F</td>
</tr>
<tr>
<td>3.568</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s1/I0</td>
</tr>
<tr>
<td>4.085</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s1/F</td>
</tr>
<tr>
<td>4.322</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_2_s0/I0</td>
</tr>
<tr>
<td>4.839</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_2_s0/F</td>
</tr>
<tr>
<td>5.076</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/I0</td>
</tr>
<tr>
<td>5.593</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/F</td>
</tr>
<tr>
<td>5.830</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/I0</td>
</tr>
<tr>
<td>6.379</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/COUT</td>
</tr>
<tr>
<td>6.379</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/CIN</td>
</tr>
<tr>
<td>6.414</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/COUT</td>
</tr>
<tr>
<td>6.414</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/CIN</td>
</tr>
<tr>
<td>6.449</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/COUT</td>
</tr>
<tr>
<td>6.449</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/CIN</td>
</tr>
<tr>
<td>6.484</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/COUT</td>
</tr>
<tr>
<td>6.484</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/CIN</td>
</tr>
<tr>
<td>6.519</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/COUT</td>
</tr>
<tr>
<td>6.519</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/CIN</td>
</tr>
<tr>
<td>6.555</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/COUT</td>
</tr>
<tr>
<td>6.555</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/CIN</td>
</tr>
<tr>
<td>6.590</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/COUT</td>
</tr>
<tr>
<td>6.590</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/CIN</td>
</tr>
<tr>
<td>6.625</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/COUT</td>
</tr>
<tr>
<td>6.625</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_8_s/CIN</td>
</tr>
<tr>
<td>6.660</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_8_s/COUT</td>
</tr>
<tr>
<td>6.660</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_9_s/CIN</td>
</tr>
<tr>
<td>7.130</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_9_s/SUM</td>
</tr>
<tr>
<td>7.367</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_9_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_dma_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_dma_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>217</td>
<td>I_dma_clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_9_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_9_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>10</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 4.377, 67.284%; route: 1.896, 29.149%; tC2Q: 0.232, 3.567%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.496</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.332</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_dma_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>I_dma_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_dma_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_dma_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>217</td>
<td>I_dma_clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>8</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s12/AD[0](chk_dup)</td>
</tr>
<tr>
<td>1.849</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s12/DO[0]</td>
</tr>
<tr>
<td>2.086</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_7_s2/I1</td>
</tr>
<tr>
<td>2.641</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_7_s2/F</td>
</tr>
<tr>
<td>2.878</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s0/I2</td>
</tr>
<tr>
<td>3.331</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s0/F</td>
</tr>
<tr>
<td>3.568</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s1/I0</td>
</tr>
<tr>
<td>4.085</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s1/F</td>
</tr>
<tr>
<td>4.322</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_2_s0/I0</td>
</tr>
<tr>
<td>4.839</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_2_s0/F</td>
</tr>
<tr>
<td>5.076</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/I0</td>
</tr>
<tr>
<td>5.593</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/F</td>
</tr>
<tr>
<td>5.830</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/I0</td>
</tr>
<tr>
<td>6.379</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/COUT</td>
</tr>
<tr>
<td>6.379</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/CIN</td>
</tr>
<tr>
<td>6.414</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/COUT</td>
</tr>
<tr>
<td>6.414</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/CIN</td>
</tr>
<tr>
<td>6.449</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/COUT</td>
</tr>
<tr>
<td>6.449</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/CIN</td>
</tr>
<tr>
<td>6.484</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/COUT</td>
</tr>
<tr>
<td>6.484</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/CIN</td>
</tr>
<tr>
<td>6.519</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/COUT</td>
</tr>
<tr>
<td>6.519</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/CIN</td>
</tr>
<tr>
<td>6.555</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/COUT</td>
</tr>
<tr>
<td>6.555</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/CIN</td>
</tr>
<tr>
<td>6.590</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/COUT</td>
</tr>
<tr>
<td>6.590</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/CIN</td>
</tr>
<tr>
<td>6.625</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/COUT</td>
</tr>
<tr>
<td>6.625</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_8_s/CIN</td>
</tr>
<tr>
<td>7.095</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_8_s/SUM</td>
</tr>
<tr>
<td>7.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_8_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_dma_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_dma_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>217</td>
<td>I_dma_clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_8_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_8_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>10</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 4.341, 67.107%; route: 1.896, 29.307%; tC2Q: 0.232, 3.586%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.531</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.297</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_dma_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>I_dma_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_dma_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_dma_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>217</td>
<td>I_dma_clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>8</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s12/AD[0](chk_dup)</td>
</tr>
<tr>
<td>1.849</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s12/DO[0]</td>
</tr>
<tr>
<td>2.086</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_7_s2/I1</td>
</tr>
<tr>
<td>2.641</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_7_s2/F</td>
</tr>
<tr>
<td>2.878</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s0/I2</td>
</tr>
<tr>
<td>3.331</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s0/F</td>
</tr>
<tr>
<td>3.568</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s1/I0</td>
</tr>
<tr>
<td>4.085</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s1/F</td>
</tr>
<tr>
<td>4.322</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_2_s0/I0</td>
</tr>
<tr>
<td>4.839</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_2_s0/F</td>
</tr>
<tr>
<td>5.076</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/I0</td>
</tr>
<tr>
<td>5.593</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/F</td>
</tr>
<tr>
<td>5.830</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/I0</td>
</tr>
<tr>
<td>6.379</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/COUT</td>
</tr>
<tr>
<td>6.379</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/CIN</td>
</tr>
<tr>
<td>6.414</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/COUT</td>
</tr>
<tr>
<td>6.414</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/CIN</td>
</tr>
<tr>
<td>6.449</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/COUT</td>
</tr>
<tr>
<td>6.449</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/CIN</td>
</tr>
<tr>
<td>6.484</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/COUT</td>
</tr>
<tr>
<td>6.484</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/CIN</td>
</tr>
<tr>
<td>6.519</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/COUT</td>
</tr>
<tr>
<td>6.519</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/CIN</td>
</tr>
<tr>
<td>6.555</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/COUT</td>
</tr>
<tr>
<td>6.555</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/CIN</td>
</tr>
<tr>
<td>6.590</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/COUT</td>
</tr>
<tr>
<td>6.590</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/CIN</td>
</tr>
<tr>
<td>7.060</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/SUM</td>
</tr>
<tr>
<td>7.297</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_7_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_dma_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_dma_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>217</td>
<td>I_dma_clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_7_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_7_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>10</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 4.306, 66.926%; route: 1.896, 29.468%; tC2Q: 0.232, 3.606%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.566</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.262</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_dma_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>I_dma_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_dma_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_dma_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>217</td>
<td>I_dma_clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>8</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s12/AD[0](chk_dup)</td>
</tr>
<tr>
<td>1.849</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s12/DO[0]</td>
</tr>
<tr>
<td>2.086</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_7_s2/I1</td>
</tr>
<tr>
<td>2.641</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_7_s2/F</td>
</tr>
<tr>
<td>2.878</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s0/I2</td>
</tr>
<tr>
<td>3.331</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s0/F</td>
</tr>
<tr>
<td>3.568</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s1/I0</td>
</tr>
<tr>
<td>4.085</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s1/F</td>
</tr>
<tr>
<td>4.322</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_2_s0/I0</td>
</tr>
<tr>
<td>4.839</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_2_s0/F</td>
</tr>
<tr>
<td>5.076</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/I0</td>
</tr>
<tr>
<td>5.593</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/F</td>
</tr>
<tr>
<td>5.830</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/I0</td>
</tr>
<tr>
<td>6.379</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/COUT</td>
</tr>
<tr>
<td>6.379</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/CIN</td>
</tr>
<tr>
<td>6.414</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/COUT</td>
</tr>
<tr>
<td>6.414</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/CIN</td>
</tr>
<tr>
<td>6.449</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/COUT</td>
</tr>
<tr>
<td>6.449</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/CIN</td>
</tr>
<tr>
<td>6.484</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/COUT</td>
</tr>
<tr>
<td>6.484</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/CIN</td>
</tr>
<tr>
<td>6.519</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/COUT</td>
</tr>
<tr>
<td>6.519</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/CIN</td>
</tr>
<tr>
<td>6.555</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/COUT</td>
</tr>
<tr>
<td>6.555</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/CIN</td>
</tr>
<tr>
<td>7.025</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/SUM</td>
</tr>
<tr>
<td>7.262</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_6_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_dma_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_dma_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>217</td>
<td>I_dma_clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_6_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_6_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>10</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 4.271, 66.744%; route: 1.896, 29.630%; tC2Q: 0.232, 3.626%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.601</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.226</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_dma_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>I_dma_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_dma_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_dma_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>217</td>
<td>I_dma_clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>8</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s12/AD[0](chk_dup)</td>
</tr>
<tr>
<td>1.849</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s12/DO[0]</td>
</tr>
<tr>
<td>2.086</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_7_s2/I1</td>
</tr>
<tr>
<td>2.641</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_7_s2/F</td>
</tr>
<tr>
<td>2.878</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s0/I2</td>
</tr>
<tr>
<td>3.331</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s0/F</td>
</tr>
<tr>
<td>3.568</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s1/I0</td>
</tr>
<tr>
<td>4.085</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s1/F</td>
</tr>
<tr>
<td>4.322</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_2_s0/I0</td>
</tr>
<tr>
<td>4.839</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_2_s0/F</td>
</tr>
<tr>
<td>5.076</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/I0</td>
</tr>
<tr>
<td>5.593</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/F</td>
</tr>
<tr>
<td>5.830</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/I0</td>
</tr>
<tr>
<td>6.379</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/COUT</td>
</tr>
<tr>
<td>6.379</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/CIN</td>
</tr>
<tr>
<td>6.414</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/COUT</td>
</tr>
<tr>
<td>6.414</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/CIN</td>
</tr>
<tr>
<td>6.449</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/COUT</td>
</tr>
<tr>
<td>6.449</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/CIN</td>
</tr>
<tr>
<td>6.484</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/COUT</td>
</tr>
<tr>
<td>6.484</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/CIN</td>
</tr>
<tr>
<td>6.519</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/COUT</td>
</tr>
<tr>
<td>6.519</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/CIN</td>
</tr>
<tr>
<td>6.989</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/SUM</td>
</tr>
<tr>
<td>7.226</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_5_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_dma_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_dma_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>217</td>
<td>I_dma_clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_5_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_5_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>9</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 4.236, 66.560%; route: 1.896, 29.794%; tC2Q: 0.232, 3.646%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
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